SoC Architect, Memory Subsystem (Principal Engineer)

Samsung•San Jose, CA

20h

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a SoC Architect, Memory Subsystem, you will drive the definition of SoC memory and cache subsystems for next-generation mobile products with a heavy focus on supporting On-Device ML. This is a senior technical lead role, you will identify and analyze emerging use cases, as well as, proposing new and innovative SoC memory architectures to efficiently support them. Your solid background in architecture foundation, detailed knowledge of cache hierarchy, memory subsystem, and SoC architecture are desired for success. You are empowered to experiment with new ideas while contributing to impactful ongoing deliverables and broadening your knowledge of whole SoC design. You are passionate about identifying, proposing, and delivering new SoC architecture and architecture features for products in new and existing markets – particularly around smartphone and mobile platforms. You enjoy performing high-level performance modeling and analysis of hardware features, applications, benchmarks, and complex uses cases. You are a domain expert in one or more technical areas. You understand and can analyze the impact of system-level architectural trade-offs (including CPU, GPU, NPU, ISP, memory subsystems, and system software). You are highly analytical and can leverage a data-driven approach to drive consensus around complex architectural proposals. You are skilled at creating necessary simulation/analysis tools to evaluate complex memory subsystem use cases such as gaming and camera use cases. You excel at delivering architecture proposals and specifications to the design team. You thrive on driving cross-company collaboration by communicating and articulating architecture proposals clearly and effectively, across audiences ranging from hardware software engineers to architecture community peers, and to technology leadership.

Requirements

15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
Extensive experience in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around CPU – memory subsystems
High proficiency in leveraging existing simulation capabilities or create new simulation capabilities where necessary
Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
Detailed knowledge of memory subsystem design to include existing/emerging JEDEC memory standards
Knowledge of in Interconnect and bus protocols – CHI/ACE interconnect experience preferred
Strong written and verbal communication skills
Knowledge of high performance, high efficiency design

Nice To Haves

Detailed knowledge of ODML for LLM as well as traditional CPU/GPU/NPU ML acceleration a big plus
Experience with the Android Ecosystem and analysis tools is a plus
Experience with Arm Architecture and ecosystem is a plus

Responsibilities

Drive the definition of SoC memory and cache subsystems for next-generation mobile products with a heavy focus on supporting On-Device ML.
Identify and analyze emerging use cases, as well as, proposing new and innovative SoC memory architectures to efficiently support them.
Performing high-level performance modeling and analysis of hardware features, applications, benchmarks, and complex uses cases.
Analyze the impact of system-level architectural trade-offs (including CPU, GPU, NPU, ISP, memory subsystems, and system software).
Leverage a data-driven approach to drive consensus around complex architectural proposals.
Creating necessary simulation/analysis tools to evaluate complex memory subsystem use cases such as gaming and camera use cases.
Delivering architecture proposals and specifications to the design team.
Driving cross-company collaboration by communicating and articulating architecture proposals clearly and effectively, across audiences ranging from hardware software engineers to architecture community peers, and to technology leadership.