SoC Architect, Coherent Interconnect

Samsung Electronics•San Jose, CA

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! Role and Responsibilities As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning. In this role, you will help define and implement innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs. Your knowledge in SoC and coherent interconnect architectures will drive cutting-edge solutions that power next-generation consumer mobile and adjacent markets. You design and develop coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g. AXI, ACE, CHI etc.). You contribute to the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics. You analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends. You seek proactive collaboration with global teams—including system architects, IP designers, and software teams—to help define and optimize SoC architectures, ensure interconnect designs meet system PPA requirements, and seamless integration of interconnect IP into SoC designs. You take initiatives on moderate-to-complex projects and help advance best practices, build trust, demonstrate ownership and open communications. Our Team The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments. Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $297,200. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). U.S. Export Control This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

Requirements

15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D
Deep expertise in SoC architecture, interconnect design, or related fields, with a focus on coherent interconnect architectures
Proficient in cache subsystems: design of coherent caches, optimization of caching policies, implementation of coherence protocols (e.g., MESI, MOESI), and balancing latency, bandwidth, and hierarchy trade‑offs
Prior experience working on Network-on-chip (NoC) designs and protocols (e.g., AXI, ACE, CHI etc.)
Experience with high-speed interface protocols such as PCIe, USB, and other standardized interfaces
Strong understanding of system-level design principles and optimization techniques
Skilled in programming languages such as C, C++, Python, and Verilog/VHDL
Solid communication and collaboration skills, with curiosity to navigate ambiguity in a fast-paced, global team environment

Nice To Haves

Knowledge of memory subsystem design, including existing and emerging JEDEC memory (LPDDR/HBM/DDR) standards
Detailed knowledge of on-device ML for LLMs and traditional CPU/GPU/NPU ML acceleration
Experience with the Android Ecosystem and analysis tools
Experience with Arm Architecture and ecosystem

Responsibilities

design and develop coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g. AXI, ACE, CHI etc.)
contribute to the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics
analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends
seek proactive collaboration with global teams—including system architects, IP designers, and software teams—to help define and optimize SoC architectures, ensure interconnect designs meet system PPA requirements, and seamless integration of interconnect IP into SoC designs
take initiatives on moderate-to-complex projects and help advance best practices, build trust, demonstrate ownership and open communications