SoC Architect, Coherent Interconnect

Samsung•San Jose, CA

19h

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning. In this role, you will help define and implement innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs. Your knowledge in SoC and coherent interconnect architectures will drive cutting-edge solutions that power next-generation consumer mobile and adjacent markets. You design and develop coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g. AXI, ACE, CHI etc.). You contribute to the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics. You analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends. You seek proactive collaboration with global teams—including system architects, IP designers, and software teams—to help define and optimize SoC architectures, ensure interconnect designs meet system PPA requirements, and seamless integration of interconnect IP into SoC designs. You take initiatives on moderate-to-complex projects and help advance best practices, build trust, demonstrate ownership and open communications.

Requirements

15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D
Deep expertise in SoC architecture, interconnect design, or related fields, with a focus on coherent interconnect architectures
Proficient in cache subsystems: design of coherent caches, optimization of caching policies, implementation of coherence protocols (e.g., MESI, MOESI), and balancing latency, bandwidth, and hierarchy trade‑offs
Prior experience working on Network-on-chip (NoC) designs and protocols (e.g., AXI, ACE, CHI etc.)
Experience with high-speed interface protocols such as PCIe, USB, and other standardized interfaces
Strong understanding of system-level design principles and optimization techniques
Skilled in programming languages such as C, C++, Python, and Verilog/VHDL
Solid communication and collaboration skills, with curiosity to navigate ambiguity in a fast-paced, global team environment

Nice To Haves

Knowledge of memory subsystem design, including existing and emerging JEDEC memory (LPDDR/HBM/DDR) standards
Detailed knowledge of on-device ML for LLMs and traditional CPU/GPU/NPU ML acceleration
Experience with the Android Ecosystem and analysis tools
Experience with Arm Architecture and ecosystem

Responsibilities

Design and develop coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g. AXI, ACE, CHI etc.).
Contribute to the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics.
Analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends.
Seek proactive collaboration with global teams—including system architects, IP designers, and software teams—to help define and optimize SoC architectures, ensure interconnect designs meet system PPA requirements, and seamless integration of interconnect IP into SoC designs.
Take initiatives on moderate-to-complex projects and help advance best practices, build trust, demonstrate ownership and open communications.