SoC Architect (Coherent Interconnect)

Samsung Electronics•Austin, TX

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities We’re seeking a highly experienced and skilled SoC Architect to lead the design and development of coherent interconnect architectures for next-generation System-on-Chip (SoC) products. As a key member of our SoC Architecture team, you will be responsible for defining and implementing innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs. You provide technical leadership and expertise in the design and development of coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g., AXI, ACE, CHI etc.). You collaborate with cross-functional teams to define and optimize SoC architectures, ensuring that interconnect designs meet system performance, power, and area requirements. You lead the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics. You analyze and optimize interconnect performance, power consumption, and area efficiency using simulation tools, modeling, and benchmarking. You work closely with various stakeholders, including system architects, IP designers, and software teams to ensure seamless integration of interconnect IP into SoC designs. You contribute to the development of technical roadmaps for coherent interconnect architectures, aligned with Samsung's strategic goals and industry trends. You mentor junior engineers and share knowledge and expertise with the team to ensure skill growth and expertise development. Our Team We’re building a new team to influence the product roadmap for a market-leading system IP solution. Our team focuses on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments. Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Requirements

15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD.
15+ years of experience in SoC architecture, interconnect design, or related fields, with a focus on coherent interconnect architectures.
In-depth knowledge of: Cache coherence protocols (e.g., MESI, MOESI, etc.) Network-on-chip (NoC) designs and protocols (e.g., AXI, ACE, CHI etc.) High-speed interface protocols (e.g., PCIe, USB, etc.) Interconnect IP design and development System-level design and optimization
Proficiency in programming languages such as C, C++, Python, and Verilog/VHDL.
Proven experience in technical leadership, collaboration, and communication with cross-functional teams.
Strong understanding of industry trends and standards in SoC architecture, interconnect design, and related technologies.

Responsibilities

Lead the design and development of coherent interconnect architectures for next-generation System-on-Chip (SoC) products.
Define and implement innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs.
Provide technical leadership and expertise in the design and development of coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g., AXI, ACE, CHI etc.).
Collaborate with cross-functional teams to define and optimize SoC architectures, ensuring that interconnect designs meet system performance, power, and area requirements.
Lead the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics.
Analyze and optimize interconnect performance, power consumption, and area efficiency using simulation tools, modeling, and benchmarking.
Work closely with various stakeholders, including system architects, IP designers, and software teams to ensure seamless integration of interconnect IP into SoC designs.
Contribute to the development of technical roadmaps for coherent interconnect architectures, aligned with Samsung's strategic goals and industry trends.
Mentor junior engineers and share knowledge and expertise with the team to ensure skill growth and expertise development.