Principal SoC Architect (ML Accelerators)

Cirrus Logic•Austin, TX

11d•Hybrid

About The Position

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldnât do it without our extraordinary workforce â and thatâs where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Are you a system-on-chip visionary, an architect who thrives at the frontier where hardware and machine learning meet? Do you want to shape the compute fabric that powers next-generation sensing, voice/image, and control at the edge? Cirrus Logicâs Technology Accelerator, Cirrus Venture Labs (CVL) may be the place for you. CVL is a newly established incubator focused on developing disruptive, scalable, and monetizable innovations that solve high-impact industry problems. Our mission is to deliver foundational silicon technologies that redefine whatâs possible for mixed-signal processing in new markets, accelerating Cirrus Logicâs diversification and strategic growth. As a Principal SoC Architect (ML Accelerators), you will play a pivotal role in defining the architectures and design tradeoffs of ML-centric SoCs that fuse analog precision, digital signal processing, and embedded machine learning. Reporting to the Head of New Business and Technology Development, you will guide the design principles for custom accelerators, memory hierarchies, and SoC fabrics optimized for our target domains, Voice/Image, Sense, and Control. You will work alongside internal and external teams, startups, and academic partners to prototype breakthrough architectures, validate them in real-world scenarios, and chart the path to scalable silicon implementation.

Requirements

Educational Background: Ph.D or Masterâs degree in Electrical Engineering, Computer Engineering, or related technical field.
Experience: 10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute.
Technical Expertise: Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization.
ISA & Compiler Co-Design: Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams to tightly couple software to hardware micro-architecture.
Mixed-Signal Awareness: Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends.
System Modeling: Strong experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis.
Prototyping Tools: Expertise with simulation, emulation, FPGA prototyping, and performance modeling frameworks.
Collaboration: Proven track record of working with cross-functional teams spanning hardware, software, research, and business.
Communication Skills: Ability to clearly articulate complex architectural concepts to both technical and non-technical audiences, including executives.

Nice To Haves

Security Architecture Expertise: Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators.
Startup/Incubator Experience: Experience driving early-stage architectural concepts from exploration through to prototype.
Low-Power Design: Expertise in energy-efficient architectures for edge workloads.
External Engagement: Strong network in academia and industry in ML accelerators, SoC design, or edge AI.
Patents & Publications: Demonstrated thought leadership through IP generation and publications in top-tier conferences/journals.
Agile & Lean Innovation: Familiarity with agile practices for rapid prototyping and early product validation.

Responsibilities

Architecture Leadership: Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends.
Cross-Domain ML Enablement: Translate domain-specific requirements (voice interaction, sensor analytics, motor control) into architectural specifications and accelerator designs.
Exploration & Tradeoff Analysis: Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis.
ISA & Compiler Co-Design: Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels.
Prototype & Validation: Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads.
Security Architecture: Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs.
Technology Scouting: Evaluate external IP, startups, and research in ML accelerators; identify opportunities for partnership, licensing, or incubation.
Advisory & Influence: Serve as a technical advisor across multiple CVL initiatives; mentor engineers, guide innovation managers, and influence long-term compute strategy.
Customer & Market Alignment: Work backwards from customer problems to ensure architectures are not only performant, but also scalable, integrable, and monetizable in real-world systems.
Thought Leadership: Publish architectural principles, drive internal alignment around ML-enabled mixed-signal processing, and represent CVL in industry and academic forums.