Signal and Power Integrity Technical Lead (Hybrid)

Cisco•San Jose, CA

5d•Hybrid

About The Position

Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead our Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

Requirements

Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and/or power integrity experience.
Proven experience with multiple high-speed ASIC tape-outs from a package perspective.
Deep expertise in 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
Extensive hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
Working knowledge of SPICE.

Nice To Haves

Prior experience leading small to medium technical teams.
Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
Experience with advanced nodes (5nm, 3nm and below).
Background in high-bandwidth memory (HBM) or high-speed memory interface SI.
Experience with die-to-die interfaces (UCIe or proprietary).
Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
Experience with MATLAB or Python scripting.
Experience with Raptor-X.
Working knowledge of Vector Network Analysis.
Basic knowledge of IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Benefits

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.