Senior Staff Engineer, Digital IC Design

Marvell TechnologySanta Clara, CA
1d$167,000 - $187,000

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect

Requirements

  • Bachelor’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.
  • Experience must include four (4) years with each of the following:
  • At least one major sub-circuit block from architecture definition to fine tuning.
  • Digital IC design methodologies - Verilog/VHDL coding.
  • AMBA AXI/AHB/APB.
  • Low power digital design techniques.
  • Optimizing small sub-circuit blocks design across Process, Voltage, Temperature.
  • Industrial standard digital design EDA tools, including LINT, CDC/RDC, VCS, Verdi, DesignCompiler, PrimeTime.
  • Scripting in Python and TCL.
  • Micro-controller firmware.

Responsibilities

  • Design and develop integrated circuits.
  • Develop Marvell's high speed SERDES and D2D IPs.
  • Conduct in-depth circuit analysis for compact sub-circuit blocks within overall design, considering Process, Voltage, and Temperature (PVT) factors.
  • Define power on/off sequence between different power states for Marvell's IPs.
  • Perform RTL design
  • Optimize performance within specified area and power constraints, utilizing engineering judgment to balance trade-offs and refine designs.
  • Write test bench and run simulation.
  • Perform iterative testing, documentation, summarization of findings, and collaboration with the global team through regular meetings, ensuring alignment within the 18-month project cycles.
  • Collaborate with analog/DSP/DV/firmware/testing engineers to deliver competitive IPs.
  • Work with back-end and layout engineers on chip-level floor-planning, power planning, macro and standard cell placement, clock tree synthesis, design rule checks and post-layout timing analysis.
  • Create design documentation, descriptions, and information to support Applications Engineers, Field Applications Engineers, Test Engineers, Production Engineers, and customers.
  • Utilize Perl scripting language.

Benefits

  • With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.
  • We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.
  • For additional information on what it’s like to work at Marvell, visit our Careers page.
  • All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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