Senior Engineer, Digital IC Design

Marvell TechnologyMorrisville, NC
1d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that are driving high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.

Requirements

  • Master’s or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Using SV, UVM, industry standard EDA tools (Synopsys VCS/Verdi).
  • Chip design, Verilog/System Verilog, and design verification.
  • Unix skills.
  • DFT methodologies, industrial standards, and practices.
  • Scripting programming, including shell, TCL, Python.
  • C, C++ programming.
  • Simulators and waveform debug tools.
  • RTL design using Verilog, including synthesis and static timing.

Responsibilities

  • Participate in design and development of integrated circuits.
  • Develop SV/UVM collateral for running verification in RTL for DFT IP at block level and full chip level.
  • Use ICL and PDL, develop patterns for use on ATE, to test various IP including high speed IO and other on-chip IP such as PLL, DRO and temperature sensor modules.
  • Assist in debugging patterns on ATE, supporting test and product engineer.
  • Use SLT and other board level platforms to prototype ATE test solutions on regular basis.
  • Work with Verilog to create necessary RTL wrappers for IP that is integrated into the design.

Benefits

  • With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.
  • We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.
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