This individual leads the team to improve engineering efficiency, product quality and responsibility of the development of test plans and the functional verification on hardware at the IP, sub-system, SoC and system/architecture level for wireless and wired technologies using an object-oriented verification language called SystemVerilog in an OVM or UVM verification environment. Perform Physical and/or Mac Layer verification in developing the methodology architectural components and verification infrastructure. Responsibilities include working with the Architects, ASIC designers and Software Engineers on SoCs for mobile handset and consumer electronic applications. Write and implement feature based test plans, debug test failures, run regression and close test plan targets. Act as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
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Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees