This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the development of test plans and the functional verification hardware at the IP, sub-system level for wireless and wired technologies using an object-oriented verification language called SystemVerilog in an UVM verification environment. Performs functional verification and develops methodology architectural components and verification infrastructure. Responsible for building functional modeling simulations, developing software, scripts, tools, and tests for various graphics, running benchmarks for different applications, and performing pre- and post-silicon verification to verify correctness and ensure power goals are met. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
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Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees