Senior Engineer II-Digital Design

Microchip-posted 1 day ago
Full-time • Mid Level
Chandler, AZ
5,001-10,000 employees
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Microchip's NCS Team is seeking an experienced Design engineer to support PHY (Physical Layer) development for our next generation of USB products. The role will include working with analog and digital engineers to create mixed-signal IPs and SoC products. As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate must be in the Chandler design center.

  • Support chip-level integration, verification, and validation teams
  • Provide design documentation, description, and information to internal customers.
  • Ability to work as part of digital, analog, and DSP design team and as part of global multi-sited Development team.
  • The candidate must possess good verbal and written skills and be able to participate in group meetings, provide project updates, and write functional and technical documents.
  • Be proactive and be willing to learn and adapt quickly in a dynamic and cross-functional environment.
  • Bachelors degree with 7.5-9 years experience in digital design with solid, hands-on experience in RTL Coding and functional verification, or Masters degree with 5-6 years experience in digital design with solid, hands-on experience in RTL Coding and functional verification
  • Must have knowledge and experience in Verilog/System Verilog design and test bench creation.
  • Must have excellent debug skills in both functional and gate level simulations
  • Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT methodology, equivalence checking and synthesis.
  • Hands-on experience required with Mentor and Synopsys CAD tools such as Questa, Design Compiler, Formality and Spyglass.
  • Knowledge in synthesis for defining timing constraints to chip-level integration team and for supporting timing closure for sub-blocks.
  • Ability to solve timing constraint challenges including asynchronous designs with multiple clock domain crossings and for synchronous designs.
  • Knowledge of ASIC test methodology such as Stuck-At/At-Speed scan insertion is a plus.
  • Proficiency in a scripting language such as C, TCL, Perl, Awk, UNIX shell.
  • Knowledge of revision control tools such as CVS, Perforce, DesignSync, etc. and experience with tagging and release methodology
  • Experience in USB and Ethernet PHY protocols is a strong plus-point.
  • Experience with Verification methodologies such as UVM/VMM is a desired skillset.
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