Senior Digital Design Engineer

NVIDIA•Santa Clara, CA

About The Position

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working engineers crafting and implementing NVLink Fusion based AI infrastructure System-on-Chips. You will get a chance to create real impact in a dynamic, industry leading, technology-focused company, while working on NVLink Fusion technology. NVLink Fusion is the enabler for the next generation of standardized rack-scale AI connectivity. What you'll be doing: As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block. Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions. What we need to see: Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering 8+ years of relevant work experience. Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc. Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc. Deep understanding of ASIC design flows and methodology Strong analytical and interpersonal skills, excellent teammate With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast. If you're a creative and autonomous professional with a genuine passion for technology, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 25, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Requirements

Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering
8+ years of relevant work experience.
Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc.
Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc.
Deep understanding of ASIC design flows and methodology
Strong analytical and interpersonal skills, excellent teammate

Responsibilities

Analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks.
Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block.
Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner
Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.