Senior Digital Design Engineer
About The Position
Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion. We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast. We have a fantastic opportunity for an experienced Senior level Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem! This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way. As Senior Digital Design Engineer at Riverlane, you will help develop our decoder IP, at the heart of our QEC Stack. You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems. Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions. You will thrive in an environment where knowledge sharing, and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change as the technology evolves, so the ability to adapt is important.
Requirements
- 5+ years of end to end design experience with complex, state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10) REQUIRED
- Experience with ASIC environments (<48nm) a plus
- Experience mentoring junior hardware design engineers
- Proven professional experience in at least one of the following areas: Customization of RISC-V CPUs e.g. addition of new instructions and associated hardware accelerators; Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo-codes; Implementation of high-speed serial communication links across multiple FPGAs, or PCIe-based communication links Implementation of quantum control systems, or quantum decoders Architecture of System on Chip (SoC) solutions, with at least one CPU and custom accelerators
- Proven capability to test, debug and improve complex systems
- Ability to convert product requirements into technical specifications to document and share your work
- A curious nature and a passion for learning and continuous improvement
- Excellent communication skills, with the ability to work both independently and collaboratively as part of a team
Nice To Haves
- Customer facing experience (technical sales, consulting experience) preferred
Responsibilities
- Implementation of QEC decoders on hardware
- Implementation of low-latency, high throughput data movement between cards and IPs
- Design of low-latency interfaces to bring data in the systems
- Mentor junior engineers (not a manager role-no direct reports)
- design end to end or integrate complex IPs and develop tests, collaborating closely with our Software, Verification and Testing experts to deliver an outstanding product.
Benefits
- A comprehensive benefits package that includes an annual bonus scheme, private health insurance, life insurance and a contributory retirement fund
- Equity, so that our team can share in the long-term success of Riverlane
- Generous annual leave, and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth and learning, including training and conference budgets
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
Number of Employees
51-100 employees
