Senior Digital Design Engineer

Analog DevicesChandler, AZ
3d

About The Position

Analog Devices Inc. is seeking a Senior-Level Digital Design Engineer to verify and design integrated circuits and support assigned products through the full product life cycle in the Power Solutions Group located in Chandler, AZ. Emphasis will be mainly on design, though verification assignments will also be available on an as-needed basis.

Requirements

  • BSEE + 4 years or MSEE + 2 years Digital IC Design experience.
  • Strong written and verbal communication skills.
  • Strong general coding and documentation skills.
  • SystemVerilog fluency in design.
  • Experience with a scripting language (Perl, Python, C, etc.)
  • Fundamental understanding of UVM
  • Ability to own and drive assignments to completion with little supervision.
  • Hands-on development, implementation, and validation of FPGA, including synthesis, timing closure, and system integration.
  • Ability to learn and master the full digital verification process (eventually covering all areas of experience listed below).

Nice To Haves

  • Working experience with custom digital interfaces (I2C, SPI, UART, etc.).
  • Design experience with custom state machines and control logic for use with analog circuits such as linear regulators, DC-DC converters, data converters, and mixed signal processing functions.
  • RTL design for synchronous applications, including multiple clock domains (asynchronous design experience a plus).
  • Logic synthesis, interfacing with place & route staff, static timing analysis, logic equivalency checking, etc.
  • Design for test, scan insertion, ATPG, functional test vectors, etc.
  • Mixed-signal simulation (Cadence AMS), interfacing with analog functions (Verilog-AMS or real number modeling experience a plus).
  • System Verilog Assertion for Dynamic and Formal Verification.
  • Verification test plan creation, coverage closure, test case, and regression suite development.
  • Advanced knowledge of complex IC verification techniques (SystemVerilog/UVM).

Responsibilities

  • Definition of interfaces, state machines, and controlling logic required to implement new products in a wide range of application spaces
  • RTL digital design and problem solving
  • Digital synthesis, place-and-route supervision, including STA, LEC, GLS, etc. tasks as needed by the project
  • Development of directed and constrained random test cases in SystemVerilog
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