Senior Digital Design Engineer (AI Fabric)

Astera Labs • San Jose, CA

2d

About The Position

Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Requirements

• Bachelor’s degree in electrical engineering or equivalent
• 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Track record of delivering high quality digital designs from definition to production.
• Experience with functional and formal verification at block and chip level.
• Understanding of clocking, CDC and RDC
• Experience with CMOS nodes (≤7nm)
• Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar
• Experience with IP development and integration
• Proven SystemVerilog and Python expertise in a production environment
• Familiarity with Synopsys and/or Cadence digital design flows
• Basic understanding of UVM-based verification methodologies
• Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
• Good communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who adapts quickly to changing requirements
• Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.

Nice To Haves

• Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
• Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 251-500 employees