Mixed Signal Engineering

Apple•San Diego, CA

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do. DESCRIPTION APPLE INC has the following available in San Diego, California. Timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints; Interacting with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. Developing ideas and plans to verify timing constraints; and Innovating timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $163,197.00 - $210,100.00/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Requirements

Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field and 4 years of experience in the job offered or related occupation.
4 years of experience with each of the following skills is required: Operating Industry EDA tools like PrimeTime, Genus, Conformal, LEQ, VCLP, Linting Tools, or CDC/RDC tools to perform IC implementation tasks such as conforming to coding styles, ensuring logical equivalence of design as it progresses, ensuring proper electrical behavior of power domains, and applying proper timing constraints in synthesis, STA, and PNR.
Utilizing PrimeTime environment to constrain design, reviewing necessary timing reports, and writing scripts to perform timing analysis tasks.
Utilizing digital IC timing closure process, from timing constraint inception to tapeout, to ensure design is specified with correct timing/frequency requirements and meeting those requirements at tapeout
Utilizing System Verilog or Verilog to read and write RTL for the high-speed communication IPs.
Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models.
Utilizing CDC, RDC tools/techniques and knowledge of multiple clock domains, multiple reset domains and fixing issues.
Utilizing upf language to define power spec and perform related low-power synthesis and verification using tools such as Genus, VCLP and LEC.

Nice To Haves

Responsibilities

Timing sign-off, STA and sign-off flow development
Ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints
Interacting with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing
Developing ideas and plans to verify timing constraints
Innovating timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis

Benefits

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs.
Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
Comprehensive medical and dental coverage
Retirement benefits
A range of discounted products and free services
For formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.
This role might be eligible for discretionary bonuses or commission payments as well as relocation.

Stand Out From the Crowd

Upload your resume and get instant feedback on how well it matches this job.

Upload and Match Resume