Resolution Enhancement Techniques Process Development Engineer

Texas Instruments Incorporated • Dallas, TX

53d

About The Position

As a Resolution Enhancement Techniques (RET) modeling engineer, you'll create and optimize OPC models for Texas Instruments' most advanced technology nodes. Models will include both lithography and etch-based models. Responsibilities will include, but are not limited to: Partnering with design, process engineering and process integration teams to define design shapes needed for building accurate models. Designing parameterized mask layouts needed for model building inputs. Investigating and implementing ML and AI methods for improving model accuracy and runtime. Implementing advanced optimization techniques. Working with process engineering and process integration teams on wafer verification to validate model quality. Working with OPC verification engineers to improve the accuracy of post-OPC verification models. These include but are not limited to weak image, assist feature printing, and resist top-loss models. Troubleshooting photolithographic patterning related issues related to OPC modeling for all fabs within TI. Developing and maintaining a suite of model quality checks for unit testing. These include but are not limited to grid checks, stability tests, OPC convergence tests, and ghost contour checks. Developing models that can support multi-patterning approaches such as SADP and LELE. The person performing this role must be capable to plan effectively, drive schedules, meet critical deadlines on multiple tasks in parallel, lead technical discussions in their area of expertise, and work effectively across organizational boundaries. They must be able to clearly communicate project status and actions. Additionally, they must be able to interface with multiple organizations and work well on a diverse team to accomplish goals.

Requirements

• Masters in Electrical Engineering, Physics, Computer Science, Chemistry or related degree.
• 10 + years experience in OPC modeling in advanced node lithography.
• Expertise in selecting and optimizing the features needed for properly sampling design spaces for building accurate models.
• Expertise in developing test requirements to validate OPC modeling solutions.
• Strong knowledge/understanding of advanced lithography simulation and RET techniques used in semiconductor manufacturing and process development.

Nice To Haves

• Ability to lead and drive advanced processes associated with double patterning techniques in 22 nm node development.
• Expertise in Synopsys ProGen modeling software.
• Demonstrated knowledge of OPC verification software packages such as ORC, LMC+, or PLRC.
• Knowledge of critical care-abouts for 28 and 22 nm node processing.
• Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software such as Cadence Virtuoso or KLayout.
• Programming experience in Unix environment.
• Understanding of OPC pattern validation methodologies and process window assessment techniques like KLA's Photolithography Wafer Qualification (PWQ).
• Demonstrated strong analytical and problem solving skills.
• Strong verbal and written communication skills.
• Ability to work in teams and collaborate effectively with people in different functions.
• Strong time management skills that enable on-time project delivery.
• Demonstrated ability to build strong, influential relationships.
• Ability to work effectively in a fast-paced and rapidly changing environment.
• Ability to take the initiative and drive for results.

Responsibilities

• Partnering with design, process engineering and process integration teams to define design shapes needed for building accurate models.
• Designing parameterized mask layouts needed for model building inputs.
• Investigating and implementing ML and AI methods for improving model accuracy and runtime.
• Implementing advanced optimization techniques.
• Working with process engineering and process integration teams on wafer verification to validate model quality.
• Working with OPC verification engineers to improve the accuracy of post-OPC verification models. These include but are not limited to weak image, assist feature printing, and resist top-loss models.
• Troubleshooting photolithographic patterning related issues related to OPC modeling for all fabs within TI.
• Developing and maintaining a suite of model quality checks for unit testing. These include but are not limited to grid checks, stability tests, OPC convergence tests, and ghost contour checks.
• Developing models that can support multi-patterning approaches such as SADP and LELE.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees