Principal Verification Engineer

Jobgether

4d•Hybrid

About The Position

As a Principal Verification Engineer, you will lead verification efforts across multiple complex product lines, ensuring designs meet the highest standards of performance and reliability. You will define advanced verification strategies, develop robust test environments, and collaborate with global teams to drive functional validation and silicon bring-up. This role emphasizes both hands-on technical expertise and leadership, allowing you to influence methodology improvements while mentoring engineers. Operating in a fast-paced, innovative environment, you will shape verification processes that ensure quality, scalability, and efficiency in cutting-edge hardware development.

Requirements

MSEE with 10+ years of verification experience or PhD with 7+ years
Advanced knowledge of SystemVerilog and UVM methodology
Proficiency with EDA tools such as VCS, Xcelium, and IMC
Strong scripting and automation skills (Python, Perl) for testbench and workflow efficiency
Excellent communication, leadership, and cross-functional collaboration skills

Nice To Haves

familiarity with SVA
regression management tools (e.g., Jenkins)
large-scale verification projects

Responsibilities

Lead verification planning and execution at both block and full-chip levels
Collaborate with architects and designers to align verification objectives with design intent
Build, enhance, and maintain UVM-based verification environments for complex designs
Track coverage metrics to ensure complete functional validation and quality assurance
Partner with lab teams to support silicon bring-up, debug, and validation processes
Drive improvements in verification methodology and mentor junior engineers