Principal Design Verification Engineer

Marvell Technology

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design Verification Team, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use highly advanced technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major hyperscaler company or telecom organization, etc. What You Can Expect In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Activities may include: • Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete. • Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues. • Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
OR Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
OR PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
Have proven experience in PCIe, NMVe and storage controller
Must have effective interpersonal and teamwork skills.
Participate in problem solving and quality improvement activities.
Demonstrate initiative and a bias for thoughtful action.
Grounded, detail-oriented, always backs up ideas with facts.
Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

Responsibilities

Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals.
Debugging failures and working with designers to resolve issues.
Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.