Principal Design Verification Engineer

Marvell Technology•Austin, TX

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Solutions partners with the world's most advanced technology companies—including leading hyperscalers, cloud data center operators, and telecom providers—to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies—all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics. In Custom Solutions, you'll collaborate with elite engineering teams across disciplines—from architecture and design through validation and production—to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure. What You Can Expect Define and drive comprehensive verification strategies and test plans for complex SoCs, subsystems, or IP blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon built in advanced process nodes (3nm, 2nm) Architect and implement sophisticated UVM-based verification environments including testbenches, reference models, scoreboards, monitors, coverage models, and protocol checkers to ensure exhaustive verification of assigned blocks Develop and execute comprehensive test plans encompassing directed tests, constrained-random scenarios, and coverage-driven verification to verify functional correctness, performance requirements, and error handling across all design features Own end-to-end verification closure including code coverage, functional coverage, and assertion coverage analysis, working with design teams to resolve coverage gaps and achieve 100% coverage goals with documented waivers Debug complex simulation failures using systematic root-cause analysis techniques, correlating RTL behavior with specifications, and partnering with designers to identify and resolve design issues efficiently Collaborate closely with logic designers, architects, DFT engineers, and physical design teams throughout the development cycle on micro-architecture reviews, test plan development, timing closure support, and gate-level simulation execution Drive verification methodology improvements by developing reusable verification components (VKITs), creating automation scripts for regression management and coverage analysis, and establishing best practices that enhance productivity across global verification teams Support multiple verification platforms including RTL simulation, emulation/FPGA prototyping, and post-silicon validation, ensuring test portability and maintaining verification infrastructure across platforms Integrate and validate third-party VIPs (Verification IP) and vendor models for industry-standard protocols, ensuring proper configuration and effective utilization within the verification environment Present verification progress, coverage results, and quality metrics to stakeholders through milestone reviews, cross-functional design reviews, and verification sign-off meetings, maintaining clear documentation throughout the verification cycle Coach and mentor junior verification engineers when necessary to develop their technical skills and achieve successful project outcomes What We're Looking For Requirements Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5-10 years of professional experience in ASIC/SoC verification, OR Master's degree and/or PhD with 3-5 years of experience Strong background in SoC verification and UVM-based testbench development using SystemVerilog, with proven experience architecting and implementing constrained-random verification environments Deep understanding of verification methodology including object-oriented programming, coverage-driven verification closure, directed and randomized testing strategies, and assertion-based verification Hands-on experience with industry-standard simulation tools including Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Questa for RTL and gate-level verification Strong scripting skills in Python, Perl, Tcl, or shell scripting for test automation, regression management, coverage analysis, and verification flow development Experience with the full verification lifecycle from test plan development through coverage closure, working across multiple verification platforms (simulation, emulation, post-silicon) Solid understanding of modern SoC architectures, industry-standard interfaces and protocols including AXI, AHB, PCIe, CXL, DDR/LPDDR, and high-speed SerDes Proven ability to work independently with minimal supervision while managing multiple priorities and meeting aggressive project schedules Excellent written and verbal communication skills with ability to present verification strategies and results to cross-functional teams including architecture, design, DFT, and physical design Strong interpersonal skills and demonstrated ability to work collaboratively in a matrix organization across global design centers and time zones Demonstrated problem-solving and critical thinking skills with ability to debug complex simulation failures and develop innovative solutions to verification challenges Preferred Qualifications Experience with formal verification tools and methodologies including connectivity checking, property verification, and equivalence checking Hands-on experience developing verification infrastructure for custom silicon, AI accelerators, or high-performance compute platforms Familiarity with advanced verification techniques including emulation/FPGA prototyping, hardware-software co-verification, and post-silicon validation support Knowledge of low-power verification methodologies including UPF (Unified Power Format) and power-aware simulation techniques Proficiency in C/C++ programming for verification infrastructure development, reference model creation, and integration with DPI-based testbench components Background in high-speed interface verification including 112G+ SerDes, PCIe Gen 6/7, CXL 3.0, or custom die-to-die interconnects Experience with memory subsystem verification including HBM, DDR/LPDDR controllers, or custom memory architectures Familiarity with verification metrics tracking, regression management systems, and continuous integration flows for large-scale SoC projects Experience mentoring junior verification engineers and contributing to verification methodology development Participation in customer-facing technical discussions and design reviews for custom ASIC development Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected]. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-JT2 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5-10 years of professional experience in ASIC/SoC verification, OR Master's degree and/or PhD with 3-5 years of experience
Strong background in SoC verification and UVM-based testbench development using SystemVerilog, with proven experience architecting and implementing constrained-random verification environments
Deep understanding of verification methodology including object-oriented programming, coverage-driven verification closure, directed and randomized testing strategies, and assertion-based verification
Hands-on experience with industry-standard simulation tools including Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Questa for RTL and gate-level verification
Strong scripting skills in Python, Perl, Tcl, or shell scripting for test automation, regression management, coverage analysis, and verification flow development
Experience with the full verification lifecycle from test plan development through coverage closure, working across multiple verification platforms (simulation, emulation, post-silicon)
Solid understanding of modern SoC architectures, industry-standard interfaces and protocols including AXI, AHB, PCIe, CXL, DDR/LPDDR, and high-speed SerDes
Proven ability to work independently with minimal supervision while managing multiple priorities and meeting aggressive project schedules
Excellent written and verbal communication skills with ability to present verification strategies and results to cross-functional teams including architecture, design, DFT, and physical design
Strong interpersonal skills and demonstrated ability to work collaboratively in a matrix organization across global design centers and time zones
Demonstrated problem-solving and critical thinking skills with ability to debug complex simulation failures and develop innovative solutions to verification challenges

Nice To Haves

Experience with formal verification tools and methodologies including connectivity checking, property verification, and equivalence checking
Hands-on experience developing verification infrastructure for custom silicon, AI accelerators, or high-performance compute platforms
Familiarity with advanced verification techniques including emulation/FPGA prototyping, hardware-software co-verification, and post-silicon validation support
Knowledge of low-power verification methodologies including UPF (Unified Power Format) and power-aware simulation techniques
Proficiency in C/C++ programming for verification infrastructure development, reference model creation, and integration with DPI-based testbench components
Background in high-speed interface verification including 112G+ SerDes, PCIe Gen 6/7, CXL 3.0, or custom die-to-die interconnects
Experience with memory subsystem verification including HBM, DDR/LPDDR controllers, or custom memory architectures
Familiarity with verification metrics tracking, regression management systems, and continuous integration flows for large-scale SoC projects
Experience mentoring junior verification engineers and contributing to verification methodology development
Participation in customer-facing technical discussions and design reviews for custom ASIC development

Responsibilities

Define and drive comprehensive verification strategies and test plans for complex SoCs, subsystems, or IP blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon built in advanced process nodes (3nm, 2nm)
Architect and implement sophisticated UVM-based verification environments including testbenches, reference models, scoreboards, monitors, coverage models, and protocol checkers to ensure exhaustive verification of assigned blocks
Develop and execute comprehensive test plans encompassing directed tests, constrained-random scenarios, and coverage-driven verification to verify functional correctness, performance requirements, and error handling across all design features
Own end-to-end verification closure including code coverage, functional coverage, and assertion coverage analysis, working with design teams to resolve coverage gaps and achieve 100% coverage goals with documented waivers
Debug complex simulation failures using systematic root-cause analysis techniques, correlating RTL behavior with specifications, and partnering with designers to identify and resolve design issues efficiently
Collaborate closely with logic designers, architects, DFT engineers, and physical design teams throughout the development cycle on micro-architecture reviews, test plan development, timing closure support, and gate-level simulation execution
Drive verification methodology improvements by developing reusable verification components (VKITs), creating automation scripts for regression management and coverage analysis, and establishing best practices that enhance productivity across global verification teams
Support multiple verification platforms including RTL simulation, emulation/FPGA prototyping, and post-silicon validation, ensuring test portability and maintaining verification infrastructure across platforms
Integrate and validate third-party VIPs (Verification IP) and vendor models for industry-standard protocols, ensuring proper configuration and effective utilization within the verification environment
Present verification progress, coverage results, and quality metrics to stakeholders through milestone reviews, cross-functional design reviews, and verification sign-off meetings, maintaining clear documentation throughout the verification cycle
Coach and mentor junior verification engineers when necessary to develop their technical skills and achieve successful project outcomes