Principal UVM Digital Verification Engineer

Draper • Cambridge, MA

1d • $95,000 - $245,000

About The Position

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com. Draper’s Digital Design Team is seeking a motivated and experienced Principal UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications. You will develop verification approaches, author and execute verification plans, and use formal analysis tools. While leading verification teams, you will define the test-bench architecture and verification approach. You will be responsible for developing methodologies and defining processes used by verification teams. You will also have the opportunity to lead multi-disciplinary teams and learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Requirements

• Proficiency in integrated circuit design
• Understanding of integrated circuits, semiconductors, and general computer architecture
• Ability to write detailed design specifications
• Ability to lead multi-disciplinary technical teams
• Excellent verbal and written communication skills
• Excellent mathematical skills
• Excellent organizational skills and attention to detail
• Excellent time management skills with the proven ability to meet deadlines
• Strong analytical and problem-solving skills
• Ability to prioritize tasks
• Demonstrate strong organization, planning, and time management skills to achieve program goals
• Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.
• Requires 7-10 years of experience with a bachelor's degree, or 5-10 years of experience with a master's degree in ASIC Hardware Engineering or related.
• Fluent in System Verilog including SVA
• Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
• Familiarity with at least one IEEE bus standard
• Experience with DDR3/DDR4, Amba Axi protocols
• Firm grasp of constrained-random testing and coverage-driven verification
• Experience with formal analysis
• Practice using Python, Perl, Bash or other scripting languages
• Ability to work in a Linux environment
• Strong analysis and problem-solving skills

Nice To Haves

• Experience with low power circuit design
• Experience with CMOS advanced nodes below 32nm
• Experience with radiation-hardened electronics

Responsibilities

• Design and simulate circuits at transistor-level to implement architecture and requirement specifications
• Contribute to system-level design
• Optimize hardware designs for performance, power, and cost
• Evaluate the hardware feasibility of complex algorithms and requirements
• Independently contribute to complex chip architectures and designs
• Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
• Contribute to business development and proposal activities
• Develop, document, and teach best practices to less experienced engineers
• Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics, contribute to design-for-test development.
• Develop verification approaches, author and execute verification plans, and use formal analysis tools.
• While leading verification teams, you will define the test-bench architecture and verification approach.
• You will be responsible for developing methodologies and defining processes used by verification teams.
• Develop verification and test plans
• Develop UVM Agents for proprietary buses
• Instantiate VIPs for industry standard buses
• Work in both block-level/chip-level UVM testbench environment
• Work with RTL designers to resolve simulation issues
• Implement cover groups according to design requirements
• Work on code and functional coverage closures to achieve 100%
• Perform code reviews and to mentor junior engineers in the group
• Perform other duties as assigned

Benefits

• Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 501-1,000 employees