Principal Engineer - Digital Verification

Microchip Technology Inc. • Allentown, PA

1d

About The Position

Microchip’s Data Center Solutions (DCS) Business Unit offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Principal Engineer-Verification, you will provide leadership in the highly successful PCIe Switch product line. These complex 800M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments. As a Principal Engineer-Verification, your job will entail the following: Defining verification plans and building verification environments for chip/module level designs using System Verilog with UVM. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Simulations using Cadence Incisive Enterprise Simulator, and debugging using SimVision. Writing test cases, checkers and coverage that implement the verification test plan. Support emulation, ASIC lab validation including lab debug and providing root-cause simulations and workarounds.

Requirements

• Minimum BSEE and of 10 years related proven verification or silicon design experience
• RTL verification using coverage driven verification techniques
• Scripting in any language
• Proficient in HDL languages SystemVerilog, Verilog or VHDL
• Familiarity with UNIX environment
• Good analytical, oral and written communication skills
• Able to write clean, readable, and maintainable code
• Self-motivated, proactive team player

Nice To Haves

• Programming experience or coursework in C, C++
• Experience or academic knowledge of the design and verification of interfaces and controllers for high speed serial protocols such as Serial Attached SCSI, Serial ATA, and PCI-Express
• Understanding of ASIC designs and verification methodologies
• Knowledge of MIPS or ARM, X86 system architecture

Responsibilities

• Defining verification plans and building verification environments for chip/module level designs using System Verilog with UVM.
• Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Simulations using Cadence Incisive Enterprise Simulator, and debugging using SimVision.
• Writing test cases, checkers and coverage that implement the verification test plan.
• Support emulation, ASIC lab validation including lab debug and providing root-cause simulations and workarounds.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal