Principal Engineer, PCIe Verification (AI2441)

SiMa Technologies, Inc.•San Jose, CA

53d•$220,000 - $296,400•Onsite

About The Position

The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. Will also be involved in PCIe bring-up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe bring up in Simulation, emulation and on silicon. Work on UCIe interface verification on next generation projects. Job Description: As the PCIe Design Verification Engineer, you will Participate in PCIe architecture, micro-architecture, feature discussions and reviews. Define and develop PCIe test bench components using UVM & System Verilog. Bring up and testing of PCIe in block and full-chip test environment. Develop and execute a test plan. Verification execution of PCIe EP/RC functionality and performance measurements. Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure. Manage debug of test and regression failures, as well emulation failures. Work closely with the Architecture, MLSoC Hardware and MLA Software teams. Work with emulation and MLSoC Software team to bring up and debug PCIe. Work in the lab on PCie interface silicon debug with software and systems team as and when needed.

Requirements

BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug.
Very good current working experience of UVM and System Verilog based verification methodology is a must.
Working experience on PCIe protocols Gen4/5.
Working experience on PCIe bring-up and debug on Silicon is a plus.
Past working experience on UCIe protocols is a plus.
Proficiency in C/C++/Python programming is a plus.
Good debug and problem solving skill.
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Responsibilities

Participate in PCIe architecture, micro-architecture, feature discussions and reviews.
Define and develop PCIe test bench components using UVM & System Verilog.
Bring up and testing of PCIe in block and full-chip test environment.
Develop and execute a test plan.
Verification execution of PCIe EP/RC functionality and performance measurements.
Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
Manage debug of test and regression failures, as well as emulation failures.
Work closely with the Architecture, MLSoC Hardware and MLA Software teams.
Work with emulation and MLSoC Software team to bring up and debug PCIe.
Work in the lab on PCie interface silicon debug with software and systems team as and when needed.