Principal RTL Verification Engineer

Impinj•Seattle, WA

4d•$179,700 - $269,600

About The Position

Impinj is a leading RAIN RFID provider and Internet of Things pioneer. We’re inventing ways to connect every thing to the Internet — including retail apparel, retail general merchandise, healthcare items, automobile parts, airline baggage, food and much more. With more than 100 billion items connected to date, and multiple Fortune 500 enterprises around the world using our platform, we solve for a better understanding of our world. If it’s a thing, we’re working to connect it. Join Impinj and help us realize our vision of a boundless IoT— connecting trillions of everyday items to the Internet. Team Overview: We are looking for a Principal RTL Verification Engineer to join the Impinj Reader IC Engineering team and own the IP and SoC Verification Methodologies and Environment (tools, and flows) and Lead the SoC verification for Impinj’s next generation of Reader ICs. In this position, you will use your experience in RTL Verification to take Impinj’s next generation of Reader ICs from concept through to production.

Requirements

Bachelor’s degree in electrical or computer engineering, or equivalent practical experience
15+ years of relevant industry experience; coursework in computer architecture preferred
Extensive experience in mixed signal IP and SoC RTL verification for complex multi clock and multi-power domain SoCs with complex reset and power bring-up sequences using UVM and UPF methodologies
Expertise creating and implementing RTL functional and AMS verification test plans
Experience in the implementation and verification of microcontroller microarchitectures and complex finite-state machines
Experience defining and developing bus functional models, subsystem behavioral models and architectural checkers
Experience verifying integration of external IP blocks
Demonstrated expertise in creating a unified testing approach and integration strategy to enable verification of IPs, SoC, and software Firmware inclusive of production DFT patterns
Hands-on experience developing System Verilog based Digital Mixed-Signal functional test benches using real numbered models, SV assertions, re-usable sequences, and coverage monitors for Metric Driven verification
Proven experience bringing multiple complex Mixed-Signal IP and SoC designs from concept through tape-out
Familiarity with CI/CD systems and RTL coverage tools
Scripting proficiency in Perl, Python, Ruby, or UNIX shell
Excellent written and verbal communication skills
Excellent teamwork and mentoring skills

Responsibilities

Own the development of a UVM based IP and SoC verification framework for Impinj’s next-generation RAIN RFID Reader ICs to assure A0 production worthy silicon
Deliver a parameterized, modular, scalable verification, validation methodology and automation framework, enabling AMS and Digital IPs to be seamlessly integrated across different Reader IC SoC products (Handheld versus fixed Reader)
Lead the definition and development of verification infrastructure such as coverage tools, bus functional models, subsystem behavioral models, RTL code, and System Verilog based test benches
Leverage your knowledge of advanced analog modeling techniques to enable efficient mixed signal co-simulation and quantifiable analog coverage
Lead verification of externally and internally sourced IP blocks
Review and evaluate design verification plans developed by other engineers
Work with systems and hardware teams to develop and extend HW/SW co-simulation capabilities to enable verification of Reader firmware prior to A0 tape-out
Work with RAIN RFID End-Point IC verification team to enable system verification and emulation
Mentor Reader IC verification engineer team members
Collaborate across logic, analog, test, and systems engineering teams to deliver new features and products to market
Provide project planning and budgetary input on verification tooling requirements
Support continuous improvement of existing RAIN RFID products through feature and performance enhancements