PCIe Verification Design Engineer

Advanced Micro Devices, Inc•Longmont, CO

14h•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The focus of this role is to plan, build, and execute the verification and validation of new and existing features for AMD’s programmable devices and focuses on PCIe/CXL, DMA, and associated solution IPs. THE PERSON: You have a passion for modern, complex SoC architecture, digital design, verification, and validation. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. It's expected that the candidate is very strong in one area of design/verification/validation, but should have exposure to all aspects and be knowledgeable about each one to some degree.

Requirements

Proficient in complex IP ownership; preferably in high speed I/O like PCIe/CXL, DDR, Ethernet, Video
Proficient in debugging firmware and RTL code using simulation and/or emulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with SystemVerilog
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment.
Exposure to simulation profile and efficiency improvement.
Strong background EDA tools preferably on Linux
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Scripting language experience: TCL, Python, Bash, CSH.
Familiar with FPGA and Adaptive SOC architectures and development tools.

Responsibilities

Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified
Architect moderate-complexity (one or two engineers as owners) RTL designs to integrate into the larger SoC
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build directed and random verification tests using class based verification techniques; preferably UVM
Debug simulation, in-lab, or production system failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements