Principal Engineer, ASIC Physical Design

Ayar Labs • San Jose, CA

36d • Onsite

About The Position

The ASIC Physical Design Engineer is responsible for the physical design and integration of complex SoCs with custom circuits, digital circuits, and photonics components as part of a high-speed electro-optical engine. The position focuses on the synthesis, place and route, timing closure, and physical verification steps of the design implementation process. As a Principal Engineer, the candidate is expected to take on full end-to-end responsibility for the implementation of complex blocks integrating both high-speed digital and custom blocks in leading edge process nodes. Each physical design engineer is expected to coordinate and drive activities across multiple design domains to ensure signoff design quality and timely design execution.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related fields
• 10+ years of work experience in ASIC physical design
• History of leading successful block implementations integrating custom IP in leading edge process nodes
• Proficient in Verilog RTL
• Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS) tools and flows
• Mastery of timing constraints and deep understanding of static timing analysis
• Proficient in clock tree synthesis methodologies and customization
• Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
• Proficient in ASIC signoff methodologies, checklists, and requirements
• Proficient in scripting or programming languages

Nice To Haves

• Working knowledge of the Cadence Virtuoso design environment for manual schematic entry and layout
• Programming experience in Python
• Experience with 3DIC implementation methodologies and custom tool flows
• Knowledge of high-speed SerDes or SerDes components
• Experience working in conjunction with external ASIC services providers
• Performed silicon debug and triage of physical design-related issues

Responsibilities

• Physical design of blocks containing digital and custom analog / mixed-signal blocks
• Contribute to design for test (DFT) methodologies
• Contribute to automated design methodologies for ASIC physical design
• Perform ASIC physical design (synthesis, place-and-route), static timing analysis (STA), and physical verification (DRC/LVS) of mixed-signal SoCs
• Coordinate and drive activities across multiple designers
• Contribute across a broad range of CAD methodologies to improve design implementation flows

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Publishing Industries
• Number of Employees: 101-250 employees