Principal Design Engineer, NVEG
About The Position
The Non-Volatile Engineering Group (NVEG) at Micron contributes to the development of memory products that are best-in-class in terms of die size, performance, reliability, and power. Our NVEG organization is dedicated to advancing non-volatile memory technologies such as NAND. Our primary mission is to innovate and develop groundbreaking solutions that improve the performance and reliability of non-volatile memory products. The Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines.
Requirements
- BS or MS in Electrical Engineering with 8+ years of relevant experience
- Experience in physical design flows and optimization, top-level IO blocks floorplan, and high-speed interfaces for NAND and training features
- Advanced knowledge and understanding of high-speed IO circuit performance, power and area optimization, and chip architecture/floorplan
- Experience with managing complex design projects, effectively communicating progress and outcomes
Nice To Haves
- Hands-on experience in utilizing AI to improve quality of design and efficiency
- Experience in DRAM interface (e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) as well as other industry standard interfaces
- Experience in chip level PDN optimization, signal/power integrity, power delivery network design, and physical design
- Comprehensive understanding of CMOS BSIM model, CMOS targets for high speed IO operation, and CMOS device reliability
Responsibilities
- Manage major IO/datapath block(e.g. input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipeline) to meet specifications and verify functionality and performance
- Model parasitics on layout and optimize signal quality by layout optimization. Review layout regularly and find opportunities of improving area/power.
- Communicate with project integration and other functional teams in design on specifications of major block interfaces
- Communicate with PE to drive silicon experiments and propose and implement fixes for yield improvement and silicon debugging
- Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations
- Document and review final results with experts and stakeholders
Benefits
- Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
- We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
- Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
- Additionally, Micron benefits include a robust paid time-off program and paid holidays.
- For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Number of Employees
5,001-10,000 employees
