Principal Design Engineer

Microsoft•Mountain View, CA

About The Position

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings. Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
1+ year(s) experience working on or leading projects from beginning-to-end.
8+ years experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
7+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.
10+ years of experience in silicon development with multiple successful ASIC tape outs in deep sub-micron technologies.
Experience in at least one of the areas: 1) CPU/GPU/APU micro-architecture and Silicon IP design. 2) SOC/sub-system integration and HW/SW interfaces. 3) computer architecture – floating point data-path, high-speed control logic, memory/cache hierarchy and synchronization. 4) high-throughput AXI/Router/Network-On-Chip micro-architecture and design. 5) PPA analysis and optimization. 6) RTL2PD flow and familiar with physical design/optimization toolchain.
Experience in automation using scripting languages such as Python or Perl.
Good communication, self-motivated and can collaborate with larger teams within Microsoft.

Responsibilities

Join a digital logic design team to develop AI components and sub-systems.
Define IP and sub-system micro-architecture, covering RTL entry, design quality (including Lint, CDC, RDC, power), and timing closure for high-performance IP.
Work with verification to ensure architectural compliance, and coordinate with PD, DFT, and other teams to optimize design tradeoffs.
Provide technical leadership through mentorship and teamwork.

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