Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

Amazon • Cupertino, CA

1d

About The Position

AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production.

Why this role is interesting:

- Your models are used to verify silicon before it's built — bugs you catch save months of schedule and millions of dollars
- You'll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected
- As the team scales, there's a clear path into architectural modeling — using your models to influence chip design decisions, not just validate them
- Small team, high ownership, direct impact on AWS's most strategic silicon programs

No ML background needed. You'll learn the ML accelerator domain on the job.

This role can be based in Cupertino, CA or Austin, TX.

Requirements

• Experience programming languages such as C/C++, Python, Java or Perl
• 2+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
• Familiarity with SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Nice To Haves

• 2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
• Experience working with DV teams or integrating models into verification flows
• Experience with SystemC or TLM-based modeling
• Experience correlating functional models against RTL simulation or emulation
• Experience developing or calibrating performance models
• Familiarity with Modern C++ (20 and beyond)
• Experience with PyTest, GoogleTest, or similar test frameworks
• Experience with multi-threaded simulation

Responsibilities

• Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
• Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
• Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
• Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams
• Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed