Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

Amazon • Cupertino, CA

15h

About The Position

AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production. What you'll do: - Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models - Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows - Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing - Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists - Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams - Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability Why this role is interesting: - Your models are used to verify silicon before it's built — bugs you catch save months of schedule and millions of dollars - You'll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected - As the team scales, there's a clear path into architectural modeling — using your models to influence chip design decisions, not just validate them - Small team, high ownership, direct impact on AWS's most strategic silicon programs You will thrive in this role if you: - Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks - Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models - Understand verification concepts and have worked with DV teams or in pre-silicon validation environments - Care about model fidelity and have experience correlating models against RTL or silicon - Are interested in expanding into architectural performance modeling as the team grows - Enjoy working on a small, high-impact team where you own significant pieces of the stack No ML background needed. You'll learn the ML accelerator domain on the job. This role can be based in Cupertino, CA or Austin, TX. - Experience programming languages such as C/C++, Python, Java or Perl - 2+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks) - Familiarity with SoC, CPU, GPU, and/or ASIC architecture and micro-architecture - 2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience - Experience working with DV teams or integrating models into verification flows - Experience with SystemC or TLM-based modeling - Experience correlating functional models against RTL simulation or emulation - Experience developing or calibrating performance models - Familiarity with Modern C++ (20 and beyond) - Experience with PyTest, GoogleTest, or similar test frameworks - Experience with multi-threaded simulation Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Cupertino - 165,200.00 - 223,600.00 USD annually USA, TX, Austin - 143,700.00 - 194,400.00 USD annually

Requirements

• Experience programming languages such as C/C++, Python, Java or Perl
• 2+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
• Familiarity with SoC, CPU, GPU, and/or ASIC architecture and micro-architecture
• 2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
• Experience working with DV teams or integrating models into verification flows
• Experience with SystemC or TLM-based modeling
• Experience correlating functional models against RTL simulation or emulation
• Experience developing or calibrating performance models
• Familiarity with Modern C++ (20 and beyond)
• Experience with PyTest, GoogleTest, or similar test frameworks
• Experience with multi-threaded simulation

Responsibilities

• Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
• Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
• Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
• Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams
• Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed