Senior Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

Amazon • Cupertino, CA

1d

About The Position

AWS's Trainium and Inferentia chips power the world's largest machine learning
clusters. Our team builds C++ models of these custom SoCs that RTL designers,
verification engineers, and software teams depend on throughout the silicon
development lifecycle. We're looking for a modeling engineer to build and own
models that directly impact how our chips are designed, verified, and brought to
production.

Requirements

• 6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
• Experience as a mentor, tech lead or leading an engineering team
• 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
• Experience programming in C++, using advanced language features
• Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture
• Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks
• Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models
• Understand verification concepts and have worked with DV teams or in pre-silicon validation environments
• Care about model fidelity and have experience correlating models against RTL or silicon
• Are interested in expanding into architectural performance modeling as the team grows
• Enjoy working on a small, high-impact team where you own significant pieces of the stack

Nice To Haves

• Experience working with DV teams or integrating models into verification flows
• Experience correlating functional models against RTL simulation, emulation, or silicon
• Experience developing and calibrating performance models for custom silicon
• Experience with SystemC, TLM, or cycle-approximate modeling methodologies
• Experience building regression and CI frameworks for model validation
• Familiarity with Modern C++ (20 and beyond)
• Experience with multi-threaded or distributed simulation
• ML accelerator architecture knowledge (a plus, not required)

Responsibilities

• Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
• Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
• Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
• Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams
• Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed