Physical Implementation Architect

Advanced Micro Devices, Inc•Austin, TX

19d

About The Position

As a Physical Implementation Architect, you will lead all aspects of RTL development, physical implementation during IP development to closure at SoC level, from RTL optimization through all stages of Physical Design closure. You will set technical direction, mentor engineering teams, and ensure best-in-class power, performance, and area (PPA) for high-speed (>2GHz) designs with complex I/O clocking As a Physical Implementation Architect, you will collaborate with IP architects, RTL designers, physical design engineers, and NBIO IP team managers. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team

Requirements

MS, or PhD in Electrical or Computer Engineering
15+ years of industry experience in physical implementation leadership.
Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.
Deep expertise in physical design methodologies for high-speed (>2GHz) SoCs
This role is not eligible for visa sponsorship.

Nice To Haves

Mastery of RTL optimizations to facilitate PD closures
Deep understanding of CDC, RDC, LINT, STA constraints development
Logical equivalence checking using industry standard tools
Closure of last mile timing, including functional ECO, and timing closure
Automation using TCL and Python, including use of AI for Design

Responsibilities

Lead RTL optimization for physical implementation working with RTL team, starting from Architecture to final Physical Design closure, finding appropriate tradeoff for Power, Performance, Area (PPA).
Drive methodology and execution of the overall team’s execution through all stages of implementation synthesis, floor planning, placement, clock tree synthesis, routing, full-chip timing, closure for advanced SoC projects.
Architect and implement reference methodologies and automation scripts for global SoC development.
Provide technical leadership for multiple I/O protocols, chiplet interfaces, including PCIe, UCIe, UAlink, Ethernet, and Infinity Fabric link-layer..