Physical Design and Verification Engineer

Neuralink•Austin, TX

58d

About The Position

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification.

Requirements

Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
Minimum 5 years of experience in digital physical design and verification.
Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Nice To Haves

Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below.
Experience in DFT (Design For Test) flows and ATPG.
Experience in I/O design flow in multi-voltage power domain.
Experience in building chip floor-plan including pin placement, partitions and power grid.
Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
Experience with build tools such as CMake and Bazel.
Experience with code coverage and regression setup.

Responsibilities

RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization
Physical Signoff Verification

Benefits

An opportunity to change the world and work with some of the smartest and most talented experts from different fields
Growth potential; we rapidly advance team members who have an outsized impact
Excellent medical, dental, and vision insurance through a PPO plan
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs) Temporary Employees & Interns excluded
401(k) plan Interns initially excluded until they work 1,000 hours
Parental leave Temporary Employees & Interns excluded
Flexible time off Temporary Employees & Interns excluded