Design Verification Engineer

ASML • San Diego, CA

1d • Onsite

About The Position

We are looking for a Design Verification Engineer to serve as a technical leader driving verification strategy and execution for highly complex FPGA designs. This role will architect advanced verification environments, define methodologies, and ensure best-in-class quality for ASML’s EUV Source systems. It requires deep technical expertise, leadership in verification practices, and the ability to influence design and verification decisions across teams.

Requirements

• Bachelors’ degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• 2+ years’ experience with a Bachelor’s degree.
• 0 + years’ experience with a Master’s degree.
• Understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.
• Experience with UVM for modular and reusable verification IP development.
• Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.
• Bachelors’ degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• 5+ years’ experience with a Bachelor’s degree.
• 2 + years’ experience with a Master’s degree.
• 1+ years’ experience with a PhD.
• Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management.
• Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.
• Experience with UVM for modular and reusable verification IP development.
• Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• 8+ years’ experience with a Bachelor’s degree.
• 5 + years’ experience with a Master’s degree.
• 3+ years’ experience with a PhD.
• Must possess industry experience in FPGA design verification; equivalent experience in ASIC workflows acceptable.
• Proven track record of leading verification for complex SoC or FPGA systems, including hardware bring-up and test.
• Expert-level proficiency in SystemVerilog UVM, including architecting environments and building custom components from scratch.
• Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management.
• Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.
• Deep experience with UVM for modular and reusable verification IP development.
• Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.
• Ability to architect and optimize complex verification environments for scalability and reuse.
• Advanced problem-solving and debugging skills for system-level and multi-block designs.
• Strong leadership and mentoring capabilities; able to guide teams and influence technical direction.
• Excellent communication and collaboration skills for cross-functional engagement.
• Expertise in coverage analysis and closure strategies.
• Strong organizational and planning skills for managing large verification projects.
• Experience driving methodology improvements and automation initiatives.
• Familiarity with FPGA-specific verification strategies and hardware validation.
• Ability to innovate and implement process enhancements for efficiency and quality.
• Potential candidates will meet the education and experience requirements provided on the above job description and excel in completing the listed responsibilities for this role.
• All candidates receiving an offer of employment must successfully complete a background check band any other tests that may be required.
• This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work.

Nice To Haves

• Proficiency in scripting languages (Python, Perl, or similar) for automation and flow optimization.
• Experience with UVMF for modular and reusable verification environments.
• Exposure to formal verification techniques and advanced debug methodologies.

Responsibilities

• Define and own verification strategy for large-scale, multi-block FPGA systems.
• Architect and implement advanced, reusable verification environments using SystemVerilog UVM and UVMF.
• Develop sophisticated test benches, constrained-random tests, and coverage models to achieve full functional and code coverage.
• Drive requirement traceability and compliance through robust documentation and reporting.
• Collaborate with architects, design engineers, and cross-functional teams to ensure design integrity and verification completeness.
• Lead debug efforts for complex system-level issues and root-cause analysis.
• Establish and enforce best practices for verification methodology, automation, and regression management.
• Mentor and guide junior and mid-level engineers; provide technical leadership and training.
• Influence tool adoption, methodology improvements, and process optimization across the organization.
• Other duties as assigned.

Benefits

• The Company offers employees and their families, medical, dental, vision, and basic life insurance.
• Employees are able to participate in the Company’s 401k plan.
• Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees