Design Verification Engineer

Meta-posted 3 days ago

Full-time • Mid Level

Redmond, WA

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Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Graphics IP’s optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs.
Define, track, and lead the execution of detailed test plans for the different modules and top levels.
Implement scalable test benches including checkers, reference models, assertions in System Verilog, and deploying formal verification techniques.
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality across pre- and post-Silicon product lifecycle.
Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments.
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Bachelor’s degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering or related field and
7 years of experience in the job offered or in a related occupation
Experience must include 7 years in the following: SystemVerilog, UVM methodology, C, or C++ verification
Performing IP, sub-system, or SoC level verification using SystemVerilog UVM or OVM methodologies
Using Electronic Design Automation (EDA) tools and scripting languages such as Python, TCL, Perl, or Shell for verification environment development
Designing and implementing verification infrastructure, including developing UVM-based verification environments and executing full verification cycles
Source code revision control systems such as Git, Mercurial (Hg), or SVN and
Working with SoC communication protocols such as AXI or OCP

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