Package Design Engineer

Google•Sunnyvale, CA

2d•$156,000 - $229,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI (Signal Integrity/Power Integrity), thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs. The goal is to optimize package substrate design for electrical performance, reliability, and assembly. In this role, you will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Requirements

Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
4 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or mentor expedition.
Experience in chip package substrate layout, design verification, DFM and taping out for production.
Experience in design automation and scripting.

Nice To Haves

Experience in large-scale 2.5D/3.5D advanced package design.
Experience in working with cross-functional teams including chip design, SI/PI, and PCB design teams.
Experience in physical verification flow (e.g., Layout Versus Schematic (LVS), Design Rule Checking (DRC), connectivity).
Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD).
Ability to write scripts to customize elements of the cadence or mentor workflow.

Responsibilities

Manage physical package substrate design of large form-factor package for ML High-Performance Computers (HPCs).
Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
Collaborate closely with SI/PI, Thermal, and Mechanical Engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
Define and document the requirements for the package substrate design and Bill of Materials (BOM).