Engineer 3, Integrated Circuit Package Design
About The Position
The Southwest Advanced Prototyping (SWAP) Hub is looking for a Integrated Circuit Package Design Engineer. SWAP Hub is one of eight regional innovation hubs within the Department of Defense’s Microelectronics Commons program, led by Arizona State University. SWAP Hub brings together academic, industry, and government partners to accelerate microelectronics innovation and prototyping, bridging the gap between research and scalable manufacturing for national defense and commercial applications. The IC Package Design Engineer will develop and design wafer level packages, understand design rules and package selection and work closely with our industry partner. Review customer needs, conduct reviews, layout and design work based on customer needs and work closely with manufacturing. They will be part of our expanding advanced packaging capability and directly impact our SHIELD USA objective (National Institute of Standards and Technology Substrate-based Heterogeneous Integration Enabling Leadership Demonstration for the USA), an initiative to advance microelectronics packaging. This position is funded by DoD and requires candidates to meet the definition of US person as defined in as defined by 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1.
Requirements
- Bachelor's degree and five (5) years of experience appropriate to the area of assignment/field; OR, Any equivalent combination of experience and/or training from which comparable knowledge, skills and abilities have been achieved.
- This position is funded by DoD and requires candidates to meet the definition of US person as defined in as defined by 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1.
Nice To Haves
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- Physical design (layout) at least 5+ years
- Familiarity or similar with Cadence Allegro/APD+ (preferred), Cadence Sigrity, Siemens expedition and ability to learn new tool augmentations.
- Knowledge of package level Signal integrity/ Power integrity familiarity
- Basic Understanding of the Silicon Life Cycle
- Basic Familiarity with Circuit/ layout/ DRC/LVS flows
- Ability to work across teams
- Open to learning new tools, debugging for bring up of tool flows.
- EDA tool and LINUX/UNIX knowledge and scripting languages
Responsibilities
- Package and PCB design work using Cadence Allegro/APD+ Signal Integrity a plus, HFSS a plus
- Provide feedback to customers to solve design problems and improvements
- Collate and document Advanced packaging tool needs, tool updates, compatibility and flow
- Support workshops and training of above within the various programs
- Support Circuits and Architecture microelectronics team EDA tool flow enablement, support the organization on flow changes and new methodologies
Benefits
- health, dental, and vision insurance plans
- life insurance and disability programs
- sick leave and holidays
- ASU/UA/NAU tuition reduction for the employee and qualified family members
- state and optional retirement plans
- access to ASU recreation and cultural activities
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
