Senior Circuit Design Engineer

Microsoft•San Diego, CA

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior Circuit Design Engineer to help achieve that mission. As Microsoft's cloud business continues to grow, the ability to deploy offerings and hardware infrastructure on time with high quality and low cost is of paramount importance. To achieve this goal, the Custom IP team works with architects, technologists, and design engineers to define and deliver differentiating custom IPs which bring high power, performance, and area advantages to the Azure Cloud. We are looking for a Senior Circuit Design Engineer with a passion for envisioning and creating complex technical IPs and solutions in conjunction with our SoC partners.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

5+ years of experience in SRAM or Register file design.
5+ years of experience in timing, power, EMIR characterization.
Understanding of SRAM write and read assist techniques.
Understanding of process technology and DTCO.
Understanding of layout and provide guidance to layout design.
Experience in yield and reliability.
Experience in providing technical guidance to other engineers and multitasking across multiple SoC programs.
Scripting experience in PERL, Python, or TCL.
Working knowledge of and experience in utilizing AI for circuit design tasks.
Ability to concisely communicate design value propositions and risks.
Effective debug skills.

Responsibilities

Collaborate with SoC designers to develop Memory SRAM and Register file solutions to difficult PPA challenges.
Work with internal and external process technology teams to understand and exploit advanced process DTCO knobs.
Devise methodologies for statistical analysis and timing/power/EMIR characterization.
Run quality assurance checks on IP collateral.
Develop IP and post-silicon characterization plans for inclusion on advanced process technology testchips.
Develop scripting automation for flows

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