Package Design Engineer
About The Position
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI (Signal Integrity/Power Integrity), thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs. The goal is to optimize package substrate design for electrical performance, reliability, and assembly. In this role, you will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips.
- Collaborate with SI/PI (Signal Integrity/Power Integrity), thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs.
- Optimize package substrate design for electrical performance, reliability, and assembly.
- Manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation.
- Identify and incorporate advanced chip packaging technologies into the Google chip product design pipeline.
- Contribute to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
5,001-10,000 employees
