About The Position

Complete circuit simulations using industry tools such as SPICE and Verilog. Support verification and development of schematic blocks including memory array, control logic, address decode, data path, and internal test logic. Import layout parasitic information and provide layout‑extracted netlists for required circuits. Interpret device specifications to produce die‑level circuit verification patterns and contribute to test chip definition and silicon validation planning. Collaborate in verification planning, develop verification‑compatible schematics, and assist in establishing best‑known verification practices and documentation.

Requirements

  • Bachelor's degree in Electrical or Computer Engineering.
  • Basic understanding of memory applications and CMOS fundamentals.
  • Experience with circuit simulation setup, analysis, and debug.
  • Strong written and verbal communication skills with the ability to convey complex technical concepts.
  • Demonstrated motivation to grow technical breadth and depth within collaborative global teams.

Nice To Haves

  • Experience with memory circuit design and performance optimization.
  • Familiarity with RTL, STA (Static Timing Analysis), Python, and HSPICE.
  • Exposure to silicon validation or test chip bring‑up activities.

Responsibilities

  • Complete circuit simulations using industry tools such as SPICE and Verilog.
  • Support verification and development of schematic blocks including memory array, control logic, address decode, data path, and internal test logic.
  • Import layout parasitic information and provide layout‑extracted netlists for required circuits.
  • Interpret device specifications to produce die‑level circuit verification patterns and contribute to test chip definition and silicon validation planning.
  • Collaborate in verification planning, develop verification‑compatible schematics, and assist in establishing best‑known verification practices and documentation.
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