Staff Verification Design Engineer, DRAM

Micron Technology • Boise, ID

16h

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In this position, you will collaborate with Micron’s global build and verification teams and coordinate multi-functional efforts across Product Engineering, Test, Probe, Process Integration, Assembly, CAD, and Marketing. You will proactively drive verification strategies that enable industry‑leading memory products with outstanding cost, quality, reliability, time‑to‑market, and customer satisfaction. As a Staff Verification Design Engineer at Micron Technology, Inc., you will - Develop and complete comprehensive verification plans for sophisticated memory builds, with a strong focus on DRAM products Lead and implement circuit- and system-level verification using industry-standard tools and methodologies Drive verification and development of key schematic blocks, including memory arrays, control logic, address decode, data paths, and internal test logic Perform circuit simulations using tools such as HSPICE, SPICE, Verilog, and Timing Accurate Verilog (TAV) Understand and assess the impact of architecture and design decisions on power, performance, reliability, and die size Import and analyze layout‑extracted parasitics within the circuit simulation environment Interpret device and product specifications and translate them into robust die‑level verification patterns Incorporate competitive differentiation into verification strategies through innovative concepts and methodologies Understand CMOS process reliability limits and collaborate with Technology Development to set model performance and reliability targets Lead and optimize standard‑cell and memory‑array characterization flows Support array parasitic extraction and drive the development of corresponding modeling cells Coordinate planning and review of layout‑extracted netlists for critical circuits Contribute to global Design and Verification Methodology Forums Collaborate closely with Business Units, Product Engineering, Probe, Assembly, Test, Process Integration, and CAD teams to ensure manufacturability and successful product ramp

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with equivalent professional experience accepted
• Minimum 7 years of proven experience in verification or related design roles
• Strong background in verification leadership and project coordination
• Hands‑on experience with UVM and SystemVerilog Assertions (SVA)
• Solid understanding of memory/DRAM architectures and verification challenges
• Proficiency with HSPICE and Python (required)
• Strong understanding of circuit simulation setup, analysis, and debug
• Excellent written and verbal communication skills, with the ability to convey sophisticated technical concepts to both technical and non-technical partners

Nice To Haves

• Experience with Design for Test (DFT) methodologies for memory products
• Exposure to RTL verification, Static Timing Analysis (STA), and Timing Accurate Verilog (TAV)
• Experience with silicon validation, test chip bring‑up, or post‑silicon debug
• Demonstrated ability to mentor engineers and influence verification strategy across global teams
• Strong motivation to grow technical breadth and depth within a collaborative, fast‑paced environment

Responsibilities

• Develop and complete comprehensive verification plans for sophisticated memory builds, with a strong focus on DRAM products
• Lead and implement circuit- and system-level verification using industry-standard tools and methodologies
• Drive verification and development of key schematic blocks, including memory arrays, control logic, address decode, data paths, and internal test logic
• Perform circuit simulations using tools such as HSPICE, SPICE, Verilog, and Timing Accurate Verilog (TAV)
• Understand and assess the impact of architecture and design decisions on power, performance, reliability, and die size
• Import and analyze layout‑extracted parasitics within the circuit simulation environment
• Interpret device and product specifications and translate them into robust die‑level verification patterns
• Incorporate competitive differentiation into verification strategies through innovative concepts and methodologies
• Understand CMOS process reliability limits and collaborate with Technology Development to set model performance and reliability targets
• Lead and optimize standard‑cell and memory‑array characterization flows
• Support array parasitic extraction and drive the development of corresponding modeling cells
• Coordinate planning and review of layout‑extracted netlists for critical circuits
• Contribute to global Design and Verification Methodology Forums
• Collaborate closely with Business Units, Product Engineering, Probe, Assembly, Test, Process Integration, and CAD teams to ensure manufacturability and successful product ramp

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.
• For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level