Manager - Design Engineering

Microchip•Chandler, AZ

1d•Onsite

About The Position

The MPU Business Unit at Microchip Technology is searching for an Engineering Manager to oversee our high-performing Design team in Chandler, Arizona. This essential leadership position will be responsible for directing the execution and ensuring the successful launch of our upcoming MPU products featuring AI capabilities. Success in this role hinges on your ability to cultivate an environment of continuous improvement and foster exceptional team collaboration. You will work with our multi-sited global Silicon Development Team in design and development of complex SoCs. The role will involve SoC design integration, developing microarchitecture, performing design verification, and coordinating with implementation teams.

Requirements

Excellent understanding of System on Chip architectures (ARM and/or Risc-V)
Deep hands-on experience in: RTL Design (Verilog/SystemVerilog) methodologies and infrastructure Functional Verification (UVM, assertions, coverage) methodologies and infrastructure
Familiarity with industry leading EDA tools and flows.
Good Understanding of C
Strong understanding of SOC Development cycles with focus on quality, performance metrics, and progress tracking.
Superior Written and Verbal Communication skills
Experience in leading teams
Experience working with global cross functional teams
BS or MS in Electrical Engineering or related field.
Minimum 12 years of relevant experience in SoC design.
Demonstrated leadership in technical teams and cross-site collaboration.

Nice To Haves

Experience with Risc-V, NoC, DDR, PCIe, Cryptography, MIPI, Ethernet MAC & Video IPs integration.
Low Power Design knowledge.
IP/SoC Synthesis experience.
Experience in STA and timing closure.
Experience in Emulation/pre silicon validations.

Responsibilities

Interpret SoC requirements and architectural specifications while collaborating with IP, architecture, and application teams to ensure accurate integration of IPs into SoCs that meet overall chip-level requirements.
Lead Design and integration of complex IPs and subsystems into complex SoCs.
RTL Design & checks – Lint, CDC, RDC.
Support Development of verification plan for subsystems/SoC.
Overcome design challenges, support achievement of quality goals, provide debug support.
Hold spec reviews, code reviews, integration reviews, coverage analysis, etc. to meet quality goals.
Development of timing constraints and synthesis.
Power Estimation and Analysis.
Drive team building, skill improvement and performance management.
Contribute to cross-geo cooperation and positive work environment.