Logic Design Intern FPGA Design Verification Intern - Summer 2026 (Teredyne, N Reading, MA)
About The Position
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our PurposeTERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.Opportunity Overview As an intern, you will work alongside experienced design and verification engineers to help design, verify, and validate cutting‑edge FPGA‑based solutions that power our next‑generation instruments. This internship offers hands‑on exposure to real engineering challenges, modern verification methodologies, and industry‑standard tools, making it an excellent opportunity for students passionate about digital design and verification.
Requirements
- Currently enrolled in a BS or MS degree program in Electrical Engineering or Computer Engineering.
- BS students must be at Junior or Senior standing with a minimum GPA of 3.2.
- MS students must also maintain a minimum GPA of 3.2.
- Coursework must include: FPGA design using Verilog, SystemVerilog, or another HDL FPGA verification using Verilog, SystemVerilog, or another HDL
- Excellent written and verbal communication skills.
- Ability to thrive in a fast-paced engineering environment.
- Strong self‑starter mindset with the ability to identify gaps in knowledge and proactively seek answers.
- Must be available to work on-site at the North Reading, Massachusetts office.
- Must be available to work during the summer break (May–September 2026), based on school schedule.
- We are only considering candidates local to position location and are unable to provide relocation for this position.
- This position is not eligible for visa sponsorship.
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What This Job Offers
Career Level
Intern
