Design and Verification Engineering Intern, Summer 2026 (Teradyne, N Reading, MA)
About The Position
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.Opportunity OverviewTeradyne is a leading provider of ATE solutions to the world's foremost semiconductor companies.We are looking for creative FPGA/ASIC Design and Verification Engineers to join our instrumentation development teams. As an intern, individuals will work as part of a team. The roles and responsibilities of our interns will touch on FPGA/ASIC design implementation, specification analysis, and design verification. Interns participate in design reviews, failure analysis, and more broadly in achieving project goals.
Requirements
- Qualified applicants must be currently enrolled in a BS or MS degree program
- Qualified majors are EE or CE
- Must be currently enrolled in JR or SR level in BS degree program with 3.2 GPA or greater - OR Currently enrolled MS level students with minimum GPA of 3.2 or greater.
- Qualified applicants will have course work focused on FPGA/ASIC Design with verilog or other HDL, or course work focused on FPGA/ASIC Verification with verilog or other HDL
- Must be available to work on site at the North Reading, Massachusetts office as needed.
- Must be available during the summer break (May - September) based on school schedule
- Excellent written and verbal communication skills.
- Ability to work in a fast paced and challenging environment
- Self-starter. Ability to recognize gaps in his or her own knowledge and seek out answers.
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What This Job Offers
Career Level
Intern
