HBM IO Architecture, Principal Engineer

Micron • Richardson, TX

1d

About The Position

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are looking for a Principal Engineer in HBM IO Design Architecture to serve as the technical authority for IO circuit design, PHY architecture, TSV-based link design, and IO training on Micron's HBM products. You will lead complex, multi-disciplinary IO design initiatives spanning multiple HBM product generations — from TSV link scheme definition and PHY circuit architecture through IO training feature design and silicon validation. Bringing deep expertise in analog/mixed-signal CMOS build, high-speed TSV IO, and IO training algorithms, you will lead technical innovation. You will define development standards across the organization. You will ensure Micron's HBM IO architecture remains the industry benchmark for speed, power efficiency, and quality.

Requirements

• Master's or PhD in Electrical Engineering or a related field, or equivalent professional experience
• Multiple patents, trade secrets, or publications in high-speed IO, PLL, DLL, TSV interface design, or IO training
• 10+ years of hands-on design experience, including high-speed IO/PLL/DLL, TSV stack architecture, IO training validation, or PVT margin characterization on silicon
• Proven relevance on high-speed IO circuit design or analog/mixed-signal design experience (e.g., Single-ended Rx/Tx, Buffers, PLL, DLL, ADC, DCC, Phase Interpolators, Equalizers, SerDes)
• Deep expertise in analog and digital CMOS circuit design and simulation (e.g., Cadence ADE, Spectre, HSPICE)
• Familiarity with HBM, LPDDR, UCIe, or other DRAM/interface standards (JEDEC)
• Excellent communication skills with the ability to advise senior management and influence strategic technical decisions
• At least 5 years of proven experience in the Memory industry with an MS EE degree or equivalent experience. Alternatively, 7 years with a BS EE degree or equivalent experience.

Responsibilities

• Define and own the HBM IO/data path circuit architecture and design strategy across multiple product generations, spanning from pathfinding and feasibility analysis through tape-out !
• Architect and analyze HBM TSV link schemes, including TSV IO topology, electrical characteristics, signaling strategy, and parasitic co-design across the DRAM stack and interface die
• Define and drive IO training features for HBM PHY — including read/write training, delay calibration, DCC training, phase interpolator calibration, and ZQ calibration — ensuring robust PVT margin across product generations
• Architect high-speed IO circuits for the HBM interface die (Single-ended Rx/Tx, Buffers, DCC, Phase Interpolators, Equalizers), targeting industry-leading speed and power-per-bit
• Drive cross-group alignment across Design Engineering, Product Engineering, Package Engineering, and Process Development, establishing IO and TSV link design standards and reference architectures across HIG

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.
• For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 5,001-10,000 employees