Hardware & Silicon Validation Principal Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. What You Can Expect • Own and lead the overall validation strategy and execution for hardware platforms, SoCs, or subsystems from early bring‑up through production release. • Define validation architectures, test plans, and coverage metrics aligned to product requirements and standards (PCIe/PCI-SIG, IEEE Ethernet, JEDEC DDR). • Lead post‑silicon bring‑up, functional validation, stress testing, and corner-case validation across PVT conditions. • Lead board bring-up, system integration, link training, and protocol validation (PCIe, Ethernet, DDR). • Own root-cause analysis and corrective action for complex cross-domain issues involving SoC, PHY, firmware, and board. • Act as the technical point of contact for key customers through qualification, deployment, and post-FCS support. • Lead debug war rooms, provide workarounds, and deliver clear technical reports and best-practice guidelines. • Conduct customer trainings on protocols, validation workflows, and issue triage. • Partner with SoC/ASIC, PHY, Firmware/Software, Diagnostics, System Architecture, Manufacturing/CM, Program Management, and Field/Apps. • Align validation plans and risk mitigation with program schedules, quality objectives, and customer commitments. What We're Looking For We are seeking a seasoned Hardware Validation Architect to lead end-to-end validation of complex systems—including functional, electrical, board-level, production/qualification, and customer engagement—for high-performance networking and compute platforms. The ideal candidate has deep hands-on expertise across PCIe, Ethernet, and DDR (DDR4/DDR5/LPDDR5) subsystems and thrives in cross-functional environments spanning silicon, firmware, system, and manufacturing. This role is both technical and customer-facing, responsible for defining strategy, building validation frameworks, ensuring quality at scale, and guiding customers through deployment and issue resolution.

Requirements

Bachelor’s degree in computer science, Electrical Engineering or related fields and 10-15+ years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10+ years of experience.
Proven experience leading hardware or post‑silicon validation efforts for complex SoCs, ASICs, boards, or systems through multiple product cycles. Experience with production test development, manufacturing qualification, and failure analysis (FA/PA).
Hands‑on expertise validating high‑speed interfaces such as DDR (DDR4/DDR5), HBM, PCIe, Ethernet, SerDes, or similar technologies.
Solid understanding of SoC architecture, hardware–software interactions, and system‑level dependencies.
Experience validating designs against industry standards (JEDEC, PCI‑SIG, IEEE, etc.) and internal specifications.
Proficiency with lab equipment including oscilloscopes, logic analyzers, protocol analyzers, traffic generators, and power measurement tools.
Prior experience in customer-facing roles—field support, FAEs, or validation leadership for enterprise customers.
Demonstrated ability to define and own end‑to-end validation strategy, including test planning, coverage definition, execution, and sign‑off criteria.
Excellent customer-facing communication: translating complex technical findings into clear actions for high-touch customers.
Communication excellence: concise lab reports, executive-ready summaries, and customer-facing documentation.

Responsibilities

Own and lead the overall validation strategy and execution for hardware platforms, SoCs, or subsystems from early bring‑up through production release.
Define validation architectures, test plans, and coverage metrics aligned to product requirements and standards (PCIe/PCI-SIG, IEEE Ethernet, JEDEC DDR).
Lead post‑silicon bring‑up, functional validation, stress testing, and corner-case validation across PVT conditions.
Lead board bring-up, system integration, link training, and protocol validation (PCIe, Ethernet, DDR).
Own root-cause analysis and corrective action for complex cross-domain issues involving SoC, PHY, firmware, and board.
Act as the technical point of contact for key customers through qualification, deployment, and post-FCS support.
Lead debug war rooms, provide workarounds, and deliver clear technical reports and best-practice guidelines.
Conduct customer trainings on protocols, validation workflows, and issue triage.
Partner with SoC/ASIC, PHY, Firmware/Software, Diagnostics, System Architecture, Manufacturing/CM, Program Management, and Field/Apps.
Align validation plans and risk mitigation with program schedules, quality objectives, and customer commitments.