Graduate Design Verification Engineer

ARM • Austin, TX

4d • Hybrid

About The Position

Arm System IP enables designers to build Arm AMBA systems that are high-performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC. The collection of silicon proven interconnects, security IP, system controllers, debug and trace and IP tooling are all crafted, validated and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Built upon the open AMBA interface standard, we provide design teams with the foundation for building better systems. Our team is looking for highly motivated graduate design verification engineers to verify our next generation Coherent Mesh Network (CMN) family of products. What you could be doing as a Design Verification Graduate: Our verification engineers work closely with our design/architecture team to validate and release our interconnect products. Engineers are expected to work in teams in the areas of stimulus, microarchitecture checking and coverage closure on a vast area of features. Our graduate engineers work alongside our experienced team to both learn and make meaningful contributions in product development. Work on the specification and development of pre-silicon verification plans Collaborate with senior engineers to debug critical issues Training and development in the latest modern verification techniques include AI/ML, simulation and formal verification

Requirements

• Hold (or are on track to hold) a degree or equivalent experience in Computer Engineering or Electrical Engineering by August 2026. (Bachelors and Master's degrees welcome!)
• In-depth knowledge of modern computer architecture concepts and microprocessor development
• Demonstrated success in academic and/or independent projects in the field of computer architecture or digital design
• Excellent programming skills including experience with C++, SystemVerilog, SystemC TLM, Java and/or Python
• Familiarity with Linux/Unix computing environments

Nice To Haves

• Experience with UVM and/or formal verification
• Knowledge of revision control systems and large scale project development such as Git
• Knowledge or prior experience with development of test plans, debugging and coverage analysis
• Experience with modern AI tools and techniques in the area of hardware functional verification

Responsibilities

• Work on the specification and development of pre-silicon verification plans
• Collaborate with senior engineers to debug critical issues
• Training and development in the latest modern verification techniques include AI/ML, simulation and formal verification

Benefits

• In addition to a competitive salary and comprehensive rewards package, you'll also receive the support, autonomy and opportunity to excel in your career.
• With a mid-year, and year-end review you'll have two windows each year to progress recognizing the pace at which you could grow.
• Attend our 'Grad-teach-Grads' workshops, guest speaker series and various social events to expand your knowledge.
• Want to take this a step further? Join our Graduate Committee and home in on your planning, networking and co-ordination skills.
• You'll also be invited to our exclusive Global Graduate Conference (GGC)! A yearly occurrence exclusive for Graduates allowing you to hear from executive members, inspiring speakers and make connections for life.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Number of Employees: 5,001-10,000 employees