Design Verification Engineer

Niobium•Dayton, OH

17h•Remote

About The Position

Niobium Microsystems is seeking a talented and motivated Senior Design Verification Engineer to join our expanding team. The ideal candidate will have hands-on experience performing functional verification of complex SoCs using SystemVerilog and Universal Verification Methodology (UVM). As an SoC Verification Engineer, you will collaborate with a small, highly skilled team of engineers. Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team. We value individuals who possess strong problem-solving abilities and are eager to learn new processes and tools.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
Minimum of 8 years of hands-on experience in SoC verification using UVM
Experience in gate level simulation setup and process corner failure analysis
Experience using Cadence verification tools such as VCS, Verdi, and Spyglass
Experience writing and debugging RTL using SystemVerilog
Programming experience using C, C++, and/or Python/Perl
Familiarity with digital design concepts and ASIC development flow
Strong analytical and problem-solving skills
Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects
Ability to work collaboratively across teams and communicate effectively
Attention to detail and remarkable eye for accuracy
Willingness to learn and develop new skills

Nice To Haves

Experience verifying RISC-V based systems
Experience verifying high-speed interfaces such as PCIe and DDR
Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
Experience with emulation or FPGA prototyping
Experience with formal verification methodologies
Familiarity with the Chisel hardware description language

Responsibilities

Develop and execute verification plans for digital designs using SystemVerilog and UVM
Create and maintain testbenches, test cases, and test vectors
Contribute to the development of novel methodologies and verification techniques
Lead technical projects and mentorship of junior team members.
Run simulations to verify design against specifications.
Analyze results, identify issues, and debug designs
Implement coverage tracking and metrics
Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies