FPGA Design Verification Engineer

Intuitive • Sunnyvale, CA

16h

About The Position

Primary Function of Position: Verification of FPGA’s on daVinci systems for RTL functional correctness.

Requirements

• Minimum of 5 years of relevant experience and a Bachelor’s degree; or 3 years of experience and a Master’s degree; or equivalent experience
• Advanced knowledge of HVL methodology (UVM)
• Expertise in HVL and HDL (SystemVerilog, Verilog)
• Experience defining coverage space and writing coverage model
• Experience writing scripts in languages such as Perl/Python
• Solid verification skills in problem solving, constrained random testing, and debugging

Nice To Haves

• Experience with Veloce or other HW accelerators and Formal is a plus

Responsibilities

• Starting from test-planning to closing verification using coverage metrics
• Hands-on test bench development with UVM
• Working closely with the design team to review specifications and architecture, extract features, define verification plan and coverage model
• Writing constrained random tests to cover all verification scenarios
• Implementing functional cover groups, SVA to verify randomness
• Debugging failures, bug tracking, and analyzing and closing coverage

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level