Senior FPGA Verification

Quest Defense Systems & Solutions•Endicott, NY

14h•Remote

About The Position

Shape the future of innovation as we tackle cutting-edge projects that make a difference. We’re not just in the business of engineering—we’re building a brighter future. Driven by creativity and a culture of excellence, we believe in the power of engineering to solve today’s challenges and create opportunities for tomorrow. What we do matters. Quest Defense Systems and Solutions is seeking a highly skilled Senior FPGA Verification Architects with strong UVM expertise to audit, assess, and guide the completion of verification activities for multiple FPGAs in a new aerospace development program. This role is not limited to development execution; it consists of independent technical oversight , critical review of verification artifacts, and evaluation of compliance with UVM methodology and DO-254 objectives. This role will play a strategic and technical leadership role while also providing hands-on guidance to engineering teams. The role will serve as a technical expert, helping guide solution development, and ensuring alignment with client needs. This role offers the flexibility to work remotely, with occasional travel required for customer meetings, conferences, or internal events. Due to the nature of the project all applicants must be US Citizens or US lawful permanent resident .

Requirements

Bachelor’s/Master’s in EE/CE/CS
10+ years in FPGA/ASIC verification (aerospace preferred)
Significant experience performing independent technical reviews, audits, or compliance assessments – compliance reviews in line with approved cert. plan(s), checklists, coding standards, and guidelines
Deep expertise in System Verilog & UVM, including architecture-level design of UVM environments
Strong understanding of DO-254, DAL-A verification, and requirements-based testing
In-depth knowledge of UVM mechanics with ability to architect and construct UVM test benches for block and top-level verification
Experience reviewing: Verification plans UVM TB architecture Coverage models Traceability matrices Test procedures and results
Ability to review and propose corrections to the low-level test bench implementation of key requirements (interface, control/data paths, and timing)
Familiar with Questasim and advanced simulation tool constructs/methodologies including the post-processing of the results
Strong communication skills for delivering findings and corrective-action recommendations
Self-motivated, proactive, and comfortable with remote collaboration

Nice To Haves

Development of advanced UVM components (predictors, scoreboards, agents – Sequences, and monitors etc., functional coverage, and register models)
Experience with UVMF or reusable methodology frameworks
Code coverage analysis and closure strategy
Deep knowledge of UVM/UVMF mechanics to be able to lead a team concurrently developing different parts of the same testbench
Code coverage analysis for RTL Source (Statement, Branch, Focused Expression and Condition Coverage)
Ability to lead, mentor, and provide technical direction
Experience supporting board bring-up and HW/SW integration
Experience generating or reviewing DO-254 lifecycle documents
Experience with FAA/EASA SOI Audits
Experience with FPGA Validation on Target Hardware and/or creating automated test scripts for performing requirements-based testing on target hardware
Experience in using lab tools like Oscilloscope and Logic Analyzer with a good understanding of FPGA timing

Responsibilities

UVM Methodology Audit & Technical Oversight Independently evaluate UVM testbench architecture, coding practices, and component implementation (agents, monitors, scoreboards, predictors).
Review verification strategy, test plans, sequences, constraints, and coverage models for completeness and alignment with requirements.
Audit UVM processes and workflows for consistency, reuse, and methodological compliance.
Identify gaps, inefficiencies, or non-compliances in the UVM environment and recommend corrective actions.
Assess coverage closure metrics (functional, code, assertion, FSM) and report findings.
Provide guidance to distributed teams on UVM best practices, patterns, and debugging techniques.
Technical Lead experience is preferred – Ability to guide the other team member(s)
DO-254 Verification & Compliance Review and assess requirements, traceability, verification plans, and hardware lifecycle documentation.
Evaluate test cases/procedures for requirements-based adequacy.
Participate in formal reviews (PDR/CDR/VER) as an independent technical reviewer.
Audit verification artifacts for consistency with DO-254 DAL-A/B objectives.
Validate objective evidence and produce review findings and risk assessments.
Be part of the team in resolving critical findings/actions received during the customer and certification Audit(s)
Contribute to simulation, debugging, and testbench enhancements as needed.
Review RTL for correctness, coverage, and testability.